1. Field of the Invention
The invention relates to the field of address translation units for memory management, particularly in a microprocessor system.
2. Prior Art
There are many well-known mechanisms for memory management. In some systems, a larger address (virtual address) is translated to a smaller physical address. In others, a smaller address is used to access a larger memory space, for instance, by using bank switching. The present invention relates to the former category, that is, where larger virtual address is used to access a limited physical memory.
In memory management systems, it is also known to provide various protection mechanisms. For example, a system may prevent a user from writing into an operating system for perhaps even from reading the operating system to external ports. As will be seen, the present invention implements a protection mechanism as part of a broader control scheme which assigns "attributes" to data on two distinct levels.
The closest prior art known to Applicant is that described in U.S. Pat. No. 4,442,484. This patent describes the memory management and protection mechanism embodied in a commercially available microprocessor, the Intel 286. This microprocessor includes segmentation descriptor registers containing segment base addresses, limit information and attributes (e.g., protection bits). The segment descriptor table and the segment descriptor registers both contain bits defining various control mechanisms such as privilege level, types of protection, etc. These control mechanisms are described in detail in U.S. Pat. No. 4,442,484.
One problem with the Intel 286 is that the segment offset is limited to 64k bytes. It also required consecutive locations in physical memory for a segment which is not always easy to maintain. As will be seen, one advantage to the inverted system is that the segment offset is as large as the physical address space. Yet, the invented system still provides compatibility with the prior segmentation mechanism found in the Intel 286. Other advantages and distinctions between the prior art system discussed in the above-mentioned patent and its commercial realization (Intel 286 microprocessor) will be apparent from the detailed description of the present invention.